TMDXEVM5515【PDF 9/159 页】EVAL MODULE DSP FOR C55XX

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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013

2.2

2.2.1

C55x CPU

The TMS320C5515 fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation

processor core. The C55x DSP architecture achieves high performance and low power through increased

parallelism and total focus on power savings. The CPU supports an internal bus structure that is

composed of one program bus, three data read buses (one 32-bit data read bus and two 16-bit data read

buses), two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These

buses provide the ability to perform up to four data reads and two data writes in a single cycle. Each DMA

controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit

multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-

bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity

and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of

the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The

Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a

128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit

decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.

Predictive branching capability avoids pipeline flushes on execution of conditional instruction calls.

For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide

(literature number SWPU073 ).

The C55x core of the device can address 16M bytes of unified data and program space. It also addresses

64K words of I/O space and includes three types of on-chip memory: 128 KB read-only memory (ROM),

256 KB single-access random access memory (SARAM), 64 KB dual-access random access memory

(DARAM). The memory map is shown in Figure 2-1 .

On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the byte address range 000000h ? 00FFFFh and is composed of eight blocks of

4K words each (see Table 2-2 ). Each DARAM block can perform two accesses per cycle (two reads, two

writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.

Table 2-2. DARAM Blocks

CPU

BYTE ADDRESS RANGE

000000h – 001FFFh

002000h – 003FFFh

004000h – 005FFFh

006000h – 007FFFh

008000h – 009FFFh

00A000h – 00BFFFh

00C000h – 00DFFFh

00E000h – 00FFFFh

DMA CONTROLLER

BYTE ADDRESS RANGE

0001 0000h – 0001 1FFFh

0001 2000h – 0001 3FFFh

0001 4000h – 0001 5FFFh

0001 6000h – 0001 7FFFh

0001 8000h – 0001 9FFFh

0001 A000h – 0001 BFFFh

0001 C000h – 0001 DFFFh

0001 E000h – 0001 FFFFh

MEMORY BLOCK

DARAM 0 (1)

DARAM 1

DARAM 2

DARAM 3

DARAM 4

DARAM 5

DARAM 6

DARAM 7

(1)

The first 192 bytes are reserved for memory-mapped registers (MMRs). See Figure 2-1 , Memory Map

Summary.

Copyright ? 2010–2013, Texas Instruments Incorporated

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